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Microprocessor Forum 1997 - Second Day

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Microprocessor Forum 1997 - Second Day
Краткое содержание статьи: The second day of the Microprocessor Forum is filled with announcements of all the CPU manufacturers

Microprocessor Forum 1997 - Second Day

Редакция THG,  14 октября 1997
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The second day (Microprocessor Forum 1997 - First Day) of the Microprocessor Forum is filled with announcements of all the CPU manufacturers, AMD will tell us about the future of the K6, C6 will let us know what happens to the WinChip C6 in the next months and Intel will supply us with information about the Deschutes and the upcoming IA64 architecture of the Merced processor.


This year still the K6 is supposed to ship in the shrunk 0.25 micron version, which will reduce the die size from 162 mm² down to 68 mm2. This will offer higher clock speeds and the chip will require less power. 300 MHz and more will be possible, whilst the K6 will run at only 2.5 V.


The next step will be the 'K6 3D' in the first half of 1998. The K6 3D's features will be the following:

  • AMD 3D Technology
    • Instruction set extensions to accelerate 3D graphics, audio and other multimedia applications
  • Superscalar MMX Unit
    • Dual decode and dual execution pipelines
    • Maintains the K6 advantage of low execution latencies
    • No decode pairing restrictions
    • Only one cycle misalignment penalty on memory accesses
  • 100 MHz Local Bus
    • Increases local bus and L2 cache bandwidth by 50%
    • Redesigned I/O timing to allow for low cost 100 MHz motherboard
  • 9.3 Million Transistors on a Die of 81 mm²

The 3D instructions will accelerate floating point computations and multiple floating point instructions can be executed per clock. The instructions were defined and implemented in collaboration with leading ISV's. Here's some more detail:

  • SIMD (single instruction multiple data) floating point instructions
    • supports IEEE single precision data type
    • two 32-bit FP values per 64-bit reg/mem operand
    • using MMX registers
  • 24 new instruction
  • Streamlined for high performance
    • saturating arithmetic
    • no exceptions
    • limited rounding modes
    • no switching overhead between MMX and AMD-3D instructions
    • avoid x87 register stack

These new instructions will unfortunately be proprietary to AMD, although Jerry Sanders was offering to license it. Michael Slater is right to say that now it's too late, since other vendors are already going into their own directions. AMD will (have to) supply a dedicated AMD development support group for their new instructions.

The superscalar MMX unit will certainly speed up the K6's MMX performance significantly, but I was waiting for an improved and superscalar FPU as well. The 100 MHz bus speed story is nothing too new for readers of this website and we are all looking forward to it. The K6 3D is supposed to ship as a 300 MHz version initially, closely followed by a 350 MHz part. AMD plans to present K6 3D CPUs at Comdex for the first time. Let's hope I'll get one earlier.
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