<!–#set var="article_header" value="IDF Spring 2002
San Francisco – Day One” –>
Intel: CPUs in Search of a Load
At the entrance of the Intel Developer Forum, held at the Moscone Center, heightened security measures were evident – all visitor bags were thoroughly searched, just like at the airport check-in. As is traditional, Intel’s CEO Craig Barrett held the opening speech. However, instead of dishing up spectacular technology demos, plain tech fare was served instead. Barrett repeatedly emphasized how the recession-plagued economy needs fresh impetus for further growth. Among the demos that we did get, one presented feats of 3D-modelling created on the basis of several photos, using the P4/3000 and with the help of software called “Realviz”. Further details on how this software works were not mentioned. Another demonstration involved high-resolution video with a data rate of up to 60 MBit/s, which served to show off the real time playback capabilities of a P4 with 3GHz when confronted with such a data stream. To wrap up the day, there was a perspective on the next 15 years, in which Intel plans to attain a CPU clock speed of 30 GHz, based on 0.01-micron technology. All in all, the message was that there’s a lack of software that fully supports modern processors such as the Pentium 4. In Barrett’s presentation, this was somewhat tucked away between the lines, but nevertheless clear. Intel is in search of new killer applications that will increase the demand for processors with greater performance. And ideally, these applications should be as widespread as possible among the masses.
Security above all: strict bag-checking at the entrance of the Intel Developer Forum at the Moscone Center in San Francisco.
Intel: CPUs in Search of a Load, Continued
Opening speech from Intel’s CEO Craig Barrett: the chip industry currently lacks impulses. Software that uses CPUs to their full potential is rare.
At a special NDA event, Intel provided a glimpse into the 64-bit future. The focus was clearly on Itanium’s successor, McKinley, which will soon be presented with a clock speed of 1 GHz. What’s completely new is the 3 MB L3 cache – otherwise, the 64-bit processor is still based on the 0.18-micron process. It won’t be until next year that Intel will present Madison, which is based on the 0.13-micron process and fully compatible with the McKinley pin. Here, one of the highlights is the L3 cache, which will increase to 6 MB. In 2003, a debut is scheduled for a smaller variation of the 64-bit CPU, which is also based on 0.13 micron and goes by the code name “Deerfield”. The plans that were presented ended with the year 2004, where Intel will launch the Montecito, based on the 0.09 micron production process.
A view of the entrance at the Moscone Center: many seminars and events are offered.
