РЕКЛАМА
ИНФОРМАЦИЯ

Possibly Celeron for Slot1 will be abandoned !

Intel CPU Roadmap Q3/98

Q2/98

Q3/98

Q4/98

Q1/99

Q2/99

2H/99

2000
Merced
Cascades 6xx MHz
0.18 µ process
133 MHz FSB
w/256 kB full speed on-die L2 cache

Tanner 5xx MHz
2MB, 1 MB, 512 kB external full speed CSRAM L2 Cache
100 (/133 ?) MHz FSB
InTRo March 1999 (Intel estimate)

Pentium II Xeon 400-450 MHz, 2MB, 1 MB, 512 kB external full speed CSRAM L2 Cache
400 MHz w/512 or 1024 kB L2 Cache, Launch June 29, 98
450 MHz w/512tor 2048 kB L2 Cache, Launch August/September, 98

Coppermine 533 - 6xx MHz
0.18 µ process
512 kB external half speed BSRAM L2 Cache
133 MHz FSB

Katmai 450, 500 MHz

Katmai 5xx
133 FSB ?

Pentium II 350-400 MHz

Pentium II 350-450 MHz
450 MHz Launch August 24, 98

Pentium II 266-333 MHz

Pentium II 266-333 MHz

Celeron 266 (Covington Core)

Celeron 266-300 MHz
Launch June 7, 98 (Covington Core)

Celeron 266-300 MHz,
Celeron 300 'A', Celeron 333 MHz, both w/128 kB full speed on-die L2 Cache

(Mendocino Core), Launch August 24, 98

Celeron 300 'A' - 366 MHz, all w/128 full speed on-die L2 Cache, 66 MHz FSB
(Mendocino Core), 366 MHz Launch February 99
Socketed Celeron 300 'A' - 366 MHz w/128 kB cache Socketed Celeron 300 'A' - 400 MHz w/128 kB cache

Pentium MMX 200-233 MHz

mobile Pentium II 233-266 MHz

mobile Pentium II 266-300 MHz

mobile Pentium II 266-333 MHz

mobile Pentium MMX 166-266 MHz

Slot M CPUs
Slot 2 CPUs, 100 MHz front side bus
Slot 1 CPUs, 100 MHz front side bus
Slot 1 CPUs, 66 MHz front side bus
New Celeron Socket, 370pins
Socket 7 CPUs, 66 MHz system bus
Mobile CPUs, 66 MHz front side bus

The next Pentium II core at 100 MHz FSB will be Katmai, starting to ship in Q1/99, initially at 450 MHz, then soon moving to 500 MHz. Katmai will have the new MMX2 insTRuction set (old name) or 'Katmai New InsTRuctions' = KNI (pointless new name), which includes double precision floating point SIMD (single insTRuction multiple data) insTRuctions. This new insTRuction set will accelerate 3D graphics by a significant amount.

Coppermine will be a shrink of Katmai down to 0.18 µ. It will not include an on-die L2-cache, because it would otherwise interfere with Cascades. Instead of this it will continue to run with the known half speed external BSRAM L2 cache as in previous Pentium II Slot 1 CPUs. This seems more of a marketing idea rather than something that's technically necessary.

Tanner will be a Xeon with KNI, succeeding the Pentium II Xeon Slot 2 CPU, but most likely keeping its name. Tanner will include the Katmai new insTRuction set and will probably start off with 450 or 500 MHz clock speed. It will ship with 512 kB/1 MB/2 MB full speed external CSRAM L2 cache versions. I wonder what an average high speed server needs 3D enhancing insTRuctions for, but, well, I'm only a doctor and web site owner.

Cascades will not be a better, but a cheaper version of Tanner. It is a shrink of Tanner down to 0.18 µ and including a smaller 256 kB on-die L2 cache. The shrink will enable Cascades to run at 133 MHz FSB at clock speeds of more than 600 MHz.

Celeron is now available as 266 and 300 MHz version (Deschutes core), without L2 cache and running at 66 MHz FSB. On August 24 Intel will inTRoduce Celeron with 128 kB on-die L2 cache (Mendocino core) at 300 MHz (Celeron 300 'A') and 333 MHz (Celeron 333). We can expect those Celerons with L2 cache to run almost identically as fast as a Pentium II at 66 MHz FSB (Pentium II 233 - 333) with its 512 kB half speed L2 cache. The cacheless Celeron will probably disappear at the end of 1998. The second half of 1999 will eventually bring a Celeron (Mendocino core) version that will run at 100 MHz FSB, possibly starting at 350, but certainly at 400 MHz. Before that there will be a 366/66 MHz version of Celeron released around February 1999. I expect that the socketed Celeron will be available in the same speed versions as the Slot 1 model, maybe the Slot 1 Celeron will even disappear, barring a convenient upgrade path to the new Pentium II with KNI (Katmai).

The Pentium II (Klamath/Deschutes core) we have now will soon disappear. The Celeron with on-die L2 cache will first make the 66 FSB versions of the Pentium II obsolete (Pentium II 233-333), so that those will be gone by the end of 1998 or latest by the first quarter 1999. As soon as Intel starts selling Celeron at 100 MHz FSB, the Pentium II (Deschutes core!!!) at 350 and 400 MHz will become obsolete too. At this time Pentium II CPUs with Katmai core, including the new insTRuctions called KNI or previously MMX2 will be out, replacing the Pentium II CPUs with Deschutes core. As you can see, at this time the difference between Pentium II and Celeron will mainly be determined by the Celeron's lack of MMX2 or KNI as well as the top speed difference of 400 MHz for Celeron and 500 MHz for Pentium II (Katmai). This means that applications that do not use MMX2/KNI will run virtually as fast on Celeron as on a Pentium II/Katmai at the same clock speed.

The socketed Celeron will be launched in Q1/99. The idea behind this different package is nothing else but cost reduction. Slot 1 is way too expensive and too sophisticated for a solution that's as plain as the Celeron (Mendocino core with 128 kB L2 cache on die). The socket will contain 370 pins and will NOT be in any way compatible to Socket 7, which is easy to comprehend when you realize that Celeron has got the L2 cache already in the package and it's using the P6 (GTL+ protocol) instead of the Pentium bus.

Merced is not supposed to launch before 2000 now, using a new slot called 'Slot M'. A few Merced IA64 tidbits are its 'explicit parallelism', which results in several parallel machine codes after compilation of the source code. This baby runs under the name 'EPIC' for 'explicit parallel insTRuction computing'. Merced will offer 128 integer and 128 floating point registers and multiple integer and floating point units, which can all work in parallel. Intel calls this 'massive hardware resources'. IA32 is only capable of 'implicit' parallelism, resulting in one machine code after compilation. IA32 offers only 8-32 integer and 8-32 floating point registers and has only got 'few' integer and floating point units, if I'm not mistaken 'few' is an actual 'two'.
Назад
Вы читаете страницу 1 из 7
1 2 3 4 5 6 7
Далее


СОДЕРЖАНИЕ

Обсуждение в Клубе Экспертов THG Обсуждение в Клубе Экспертов THG


РЕКЛАМА
РЕКОМЕНДУЕМ ПРОЧЕСТЬ!

История мейнфреймов: от Harvard Mark I до System z10 EC
Верите вы или нет, но были времена, когда компьютеры занимали целые комнаты. Сегодня вы работаете за небольшим персональным компьютером, но когда-то о таком можно было только мечтать. Предлагаем окунуться в историю и познакомиться с самыми знаковыми мейнфреймами за последние десятилетия.

Пятнадцать процессоров Intel x86, вошедших в историю
Компания Intel выпустила за годы существования немало процессоров x86, начиная с эпохи расцвета ПК, но не все из них оставили незабываемый след в истории. В нашей первой статье цикла мы рассмотрим пятнадцать наиболее любопытных и памятных процессоров Intel, от 8086 до Core 2 Duo.

ССЫЛКИ
Реклама от YouDo
Тут https://youdo.com/lp-remont-audio-usiliteley/, подробности по ссылке.
Задача 'http://freelance.youdo.com/st91794/' на YouDo.