HOT! Update Of Intel Roadmap News!

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Intel Roadmap News 10/2000 - Part One, Desktop Processors And Chipsets

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Rambler's Top100 Рейтинг@Mail.ru


Краткое содержание статьи: Equipped with an exciting brand new design Intel's new flagship is getting ready to step out into the open. Get ready for the most controversial x86-processor of all times. Find out if you are the working class kind of guy with Athlon-ambitions or rather the stylish Yuppie that needs Pentium 4 even if it's only to be cool. Here it comes, the battle style against power.

Intel's New Pentium 4 Processor

Редакция THG,  20 ноября 2000
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The Trace Cache Branch Prediction Unit

Intel Pentium 4 Trace Cache Branch Prediction

Intel is very proud on the branch prediction unit that aids the execution trace cache. Its branch target buffer is 8 times as large as the one found in Pentium III and its new algorithm is supposed to be way better than AMD's latest G-share algorithm used in Thunderbird and Spitfire. Intel claims that this unit can eliminate 33% of the mispredictions of Pentium III.

Hyper Pipeline

Intel Pentium 4 Hyper Pipeline

One of the most well known features of the new Pentium 4 is its extremely long pipeline. While the pipeline of Pentium III has 10 stages and the one of Athlon 11, Pentium 4 has no less than 20 stages.

The reason for the longer pipeline is Intel's wish of Pentium 4 to deliver highest clock rates. The smaller or shorter each pipeline stage, the fewer transistors or 'gates' it needs and the faster it is able to run. However, there is also one big disadvantage to long pipelines. As soon as it turns out at the end of the pipeline that the software will branch to an address that was not predicted, the whole pipeline needs to be flushed and refilled. The longer the pipeline the more 'in-flight' instructions will be lost and the longer it takes until the pipeline is filled again.

Intel is proud to announce that the Pentium 4 pipeline can keep up to 126 instructions 'in-flight', amongst them up to 48 load and 24 store operations. The improved trace cache branch prediction unit described above is supposed to ensure that flushes of this long pipeline are only rare occasions.

The stuff that happens in the trace cache, as mentioned above, only represents the first five stages of the pipeline of Pentium 4. What follows is

Intel Pentium 4 Pipeline Stages

  • Allocate resources
  • Register renaming
  • Write into the µOP queue
  • Write into the schedulers and compute dependencies
  • Dispatch µOPs to their execution units
  • Read register file (to ensure that the correct ones of the 128 all-purpose register files are used as the register(s) for the actual instruction)

After that comes the actual execution of the µOP, which I will discuss more detailed in the next paragraph. Of the above-mentioned previous stages the schedulers as well as the register file read are the most interesting. I have still decided against discussing them in detail to keep this article from becoming my next book.
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Обсуждение в Клубе Экспертов THG Обсуждение в Клубе Экспертов THG


История мейнфреймов: от Harvard Mark I до System z10 EC
Верите вы или нет, но были времена, когда компьютеры занимали целые комнаты. Сегодня вы работаете за небольшим персональным компьютером, но когда-то о таком можно было только мечтать. Предлагаем окунуться в историю и познакомиться с самыми знаковыми мейнфреймами за последние десятилетия.

Пятнадцать процессоров Intel x86, вошедших в историю
Компания Intel выпустила за годы существования немало процессоров x86, начиная с эпохи расцвета ПК, но не все из них оставили незабываемый след в истории. В нашей первой статье цикла мы рассмотрим пятнадцать наиболее любопытных и памятных процессоров Intel, от 8086 до Core 2 Duo.

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