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12th Annual Hot Chips Conference in Palo Alto” –>
Introduction
The Hot Chips Conference that takes place at Stanford University in Palo Alto every summer typically focuses on new chip architectures and innovative techniques. Of course it is also about performance, clock rates, power integration and usefulness. This year the conference embraced the new ‘darling’ of the chip industry – the network processor. The two sessions included presentations from SwitchOn, SiliconAccess, EmpowerTel, Vitesse, C-Port, and IBM.
But IBM had some interesting research to talk about as well, like for example their quantum computer that is being developed in the companies’ Almaden Research Center in San Jose, CA. Scientist Isaac Chung presented a paper on a 215 Hz, 5-qubit quantum processor. It is currently the largest quantum computer in the world – a 5-bit computer in a single molecule. The molecule consists of five fluorine atoms, each representing a quantum bit, or ‘qubit’.
Chuang and his team of researchers have been working on quantum computers (QCs) since the late 1980s. His most recent success, the 5-qubit QC, is able to solve the order-finding problem, a problem related to code cracking, in a single step. The order-finding problem determines the period of a function. Digital computers must calculate the solution by using step-by-step iterations of the function’s values until they begin to repeat. The qubits take this problem to a whole new level. By nature they represent all possible values of the input variables simultaneously, hence the QC is able to consider every possible input value at once and only needs one step to solve the problem. This is the ultimate in parallel computing: parallel processing at bit level.
IBM’s quantum computer uses a molecule with five fluorine atoms, each representing 1 qubit.
According to Chuang quantum computers may someday be able to live up to their potential of solving, in remarkable short times, problems that are so complex that the most powerful supercomputers couldn’t calculate the answers even if they worked on them for millions of years.
That really made me smile because it reminded me of Douglas Adams’ sci-fi novel ‘The Hitchhiker’s Guide to the Galaxy’, which was extremely popular in my college years back in the 1980s. In one of the books a supercomputer was asked to come up with an answer to ‘the meaning of life, the universe and everything’. It took millions of years and the answer was – 42. I guess a quantum computer would have been most helpful in speeding things up a bit.
Okay – back to the serious side of science now. IBM’s latest achievement is a great success and step forward in the area of quantum computing, but it still has a long way to go before it can actually compete with digital supercomputers. For example quantum systems typically have a short lifetime, and the external control of quantum mechanics is quite difficult. Nevertheless, researchers are confident that QCs will meet this challenge within this decade. If the difficulties in connection with molecular methods can be overcome, the latter might represent an advance over silicon-circuit fabrication processes. Quantum circuits could be manufactured by using automatic controlled chemical reactions making the present definition of complex circuits obsolete. But until then processor designers and manufacturers must stick to the old-fashioned way of building chips.
Powerful
Back in the real world IBM has been working on the chip integration of their Power4 design. It is the first IBM chip that includes two processors and an L2 cache on the same die. Intended for the AS400 and RS/6000 server families, the Power4 can be used to create 32-way systems. Similar to its’ predecessor, the Power3, the processor has two floating-point units per core.
IBM’s Power4 chip has two processor cores and four floating-point units on the same die.
The Power4 is expected to run at a frequency of more than 1 GHz, and the die contains 174 million transistors. It is manufactured with 0.18-micron technology, features all-copper interconnects through seven layers of metal, and it is built using silicon-on-insulator (SOI) wafers.
According to a second paper presented at the conference, the Power4 will be able to communicate with other chips via a 500 MHz bus. The bus speeds of current designs are mostly at 100 MHz, slowly migrating to 133 MHz. IBM uses a technology called synchronous wave-pipelined interface to control and minimize the latency during the data transfer. Power4 is not in production yet, but it should be ready in 2001. Currently IBM has a test chip running in the lab.
Low Power
Transmeta, who just landed a deal with Sony, was also at the conference to announce their next-generation notebook PC microprocessor. CEO Dave Ditzel introduced the 700 MHz Crusoe TM5600, which offers twice the L2 cache than the previous TM5400 design. The package has the same pinout as the TM5400, however. The performance increases about 20 percent at the same frequency while at the same time consuming about 10 percent less power. Sony will use the Transmeta chip in selected models of its’ popular Vaio notebook product line. Even though Sony has invested in Transmeta Corporation, and thus has a vested interest in its’ success, the company says that the main incentive for using the Crusoe chip is its’ low power consumption.
