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VT82C680 APOLLO P6
Краткое содержание статьи: VT82C680 APOLLO P6 Chipset Features

VT82C680 APOLLO P6


Редакция THG,  30 августа 1996
Страница: Назад  1 2 Далее


Overview

The VT82C680 Apollo-P6 is a high performance, cost-effective and energy efficient chip set for the implementation of PCI/ISA desktop and notebook personal computer systems based on the 64-bit Intel Pentium-Pro super-scalar processors. The chipset supports multi-Pentium-Pro configuration with Intel GTL+ driver and receiver interface up to 66Mhz external CPU bus speed. The chipset supports the Pentium-Pro CPU multi-phase bus protocols for split transactions, four level deep in-order queue and deferred transactions for optimal CPU throughput.

Block Diagram

The VT82C680 chip set consists of the VT82C685 system controller, the VT82C687 data buffer and the VT82C586 PCI to ISA bridge. The VT82C680 supports six banks of DRAMs up to 1GB. The DRAM controller supports Standard Page Mode DRAM, EDO-DRAM, Burst EDO-DRAM and Synchronous DRAM in a flexible mixed/match manner. The Burst-EDO and Synchronous DRAM allows zero wait state bursting between the DRAM and the VT82C687 data buffers at 66Mhz. The six banks of DRAM allow arbitrary mixture of 1M/2M/4M/8M/16MxN DRAMs with optional bank-by-bank ECC and parity support. The chipset supports sixteen level (quadwords) of CPU to DRAM write buffers and sixteen level (quadwords) of DRAM to CPU read buffers to maximize the CPU bus and DRAM utilization. The peak data transfer rate for the EDO and Synchronous DRAM (or Burst EDO) DRAMs is 266MB/s and 532MB/s, respectively.

The VT82C680 supports 3.3/5v 32-bit PCI bus with 64-bit to 32-bit data conversion. Sixteen levels (doublewords) of post write buffers are included to allow for concurrent CPU and PCI operation. Consecutive CPU addresses are converted into burst PCI cycles with byte merging capability for optimal CPU to PCI throughput. For PCI master operation, sixteen levels (doublewords) of post write buffers and thirty-two levels (doublewords) of prefetch buffers are included for concurrent PCI bus and DRAM/cache accesses. The chipset also supports enhanced PCI bus commands such as Memory-Read-Line, Memory-Read-Multiple and Memory-Write-Invalid commands to minimize snoop overhead. In addition, the chipset supports advanced features such as snoop ahead, snoop filtering, CPU write-back forward to PCI master and CPU write-back merged with PCI post write buffers to minimize PCI master read latency and DRAM utilization. The VT82C586 PCI to ISA bridge supports four levels (doublewords) of line buffers, type F DMA transfers and delay transaction to allow efficient PCI bus utilization (PCI-2.1 compliant). The VT82C586 also includes integrated keyboard controller with PS2 mouse support, integrated DS12885 style real time clock with extended 128 byte CMOS RAM, integrated master mode enhanced IDE controller with full scatter and gather capability and extension to 33MB/sec UltraDMA-33 transfer rate, integrated USB interface with root hub and two function ports with built-in physical layer transceiver, and OnNow/ACPI compliant advanced configuration and power management interface. A complete main board can be implemented with only six TTLs.

The VT82C680 is ideal for high performance, high quality, high energy efficient and high integration desktop and notebook PCI/ISA computer systems.




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