Редакция THG,  30 августа 1996


Here are the specs of the latest Pentium Pro Chipset, just released from VIA. This chipset has the ability to defeat Intel for the first time since they released their Triton chipset. At present there is NO OTHER PPro chipset around that offers even slightly as much as this high performance chipset. If a high quality mainboard with that chipset should be out soon, I might even change my mind and get a PPro myself.

Actually I just found the first mainboard which uses the Apollo P6, it's the FIC PA-6010. Go and have a look! As soon as there's another new one out there, I'll tell you.



  • High Integration
    • VT82C685 system controller
    • VT82C687 data buffer
    • VT82C586 PCI to ISA bridge
    • Six TTLs for a complete main board implementation
  • Flexible CPU Interface
    • 64-bit Pentium-ProTM CPU interface
    • CPU external bus speed up to 66Mhz
    • Supports Pentium-ProTM CPU multi-phase bus protocol for split transactions
    • Supports four level deep in-order-queue and deferred transaction
    • Supports APICTM multiprocessor protocol
    • GTL+TM bus driver and receiver compatible with Intel specification
  • Fast DRAM Controller
    • Sixteen level (quadwords) of CPU to DRAM write buffers
    • Sixteen level (quadwords) of DRAM to CPU read buffers
    • Fast Page Mode/EDO/Burst EDO/Synchronous-DRAM support in a mixed combination
    • Mixed 1M/2M/4M/8M/16MxN DRAMs
    • Supports 2-way bank-interleaving of 16MB SDRAM
    • Supports 2-way and 4-way bank-interleaving of 64MB SDRAM
    • 6 banks up to 1GB DRAMs
    • Flexible row and column addresses
    • Optional bank-by-bank ECC and parity generation, detection, and correction capability
    • ECC with 1-bit error correction and multi-bit error detection capability
    • 3.3v and 5v DRAM without external buffers
    • Burst read and write operation
    • 5-1-1-1-1-1-1-1 back-to-back Burst EDO and Synchronous DRAM transfer at 66Mhz
    • 532MB/s peak transfer rate for Burst EDO and Synchronous DRAMs at 66Mhz
    • 266MB/s peak transfer rate for EDO DRAMs at 66Mhz
    • BIOS shadow at 16KB increment
    • System management memory remapping
    • Decoupled and burst DRAM refresh with staggered RAS timing
    • Programmable refresh rate, CAS-before-RAS refresh and refresh on populated banks only
  • Intelligent PCI Bus Controller
    • 32 bit 3.3/5v PCI interface
    • Synchronous divide-by-two PCI bus interface
    • PCI master snoop ahead and snoop filtering
    • Concurrent PCI master/CPU/IDE operations
    • Synchronous Bus to CPU clock with divide-by-two from the CPU clock
    • Automatic detection of data streaming burst cycles from CPU to the PCI bus
    • Sixteen levels (double-words) of CPU to PCI posted write buffers
    • Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities
    • Zero wait state PCI master and slave burst transfer rate
    • PCI to system memory data streaming up to 132Mbyte/sec
    • Sixteen levels (double-words) of post write buffers from PCI masters to DRAM
    • Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters
    • Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
    • Complete steerable PCI interrupts
    • Supports CPU write-back forward to PCI master read to minimize PCI read latency
    • Supports CPU write-back merged with PCI master post-write to minimize DRAM utilization
    • Provides transaction timer to fairly arbitrate between PCI masters
    • Supports five PCI masters in addition to PCI-ISA/IDE/USB bridge
    • PCI-2.1 compliant
  • Enhanced Master Mode PCI IDE Controller with Extension to UltraDMA-33
    • Dual channel master mode PCI supporting four Enhanced IDE devices
    • Transfer rate up to 22MB/sec to cover PIO mode 4 and multi-word DMA mode 2 drives and beyond
    • Extension to UltraDMA-33 interface for up to 33MB/sec transfer rate
    • Sixteen levels (doublewords) of prefetch and write buffers
    • Interlaced commands between two channels
    • Bus master programming interface for SFF-8038 rev.1.0 and Windows-95 compliant
    • Full scatter and gather capability
    • Support ATAPI compliant devices
    • Support PCI native and ATA compatibility modes
    • Complete software driver support
  • Universal Serial Bus Controller
    • USB v.1.0 and Intel Universal HCI v.1.1 compatible
    • Eighteen level (doubleword) of data FIFOs with full scatter and gather capabilities
    • Root hub and two function ports with integrated physical layer transceivers
    • Legacy keyboard and PS2 mouse support
  • Plug and Play Controller
    • Dual interrupt and DMA signal steering with plug and play control
    • Microsoft Windows 95TM and plug and play BIOS compliant
  • Sophisticated Power Management and OnNow/ACPI Unit
    • Normal, doze, sleep, suspend and conserve modes
    • System event monitoring with two event classes
    • Two general purpose timers
    • Sixteen general purpose output ports
    • Seven external event input ports with programmable SMI condition
    • Primary and secondary interrupt differentiation for individual channels
    • Clock throttling control
    • Multiple internal and external SMI sources for flexible power management models
    • APM 1.2 compliant models
    • Extension to OnNow and ACPI (Advanced Configuration and Power Interface) support
  • PCI to ISA Bridge
    • Integrated 82C206 peripheral controller
    • Integrated keyboard controller with PS2 mouse supports
    • Integrated DS12885 style real time clock with extended 128 byte CMOS RAM
    • Integrated USB controller with root hub and two function ports
    • Integrated master mode enhanced IDE controller with enhanced PCI bus commands
    • PCI-2.1 compliant with delay transaction
    • Four double-word line buffer between PCI and ISA bus
    • Supports type F DMA transfers
    • Fast reset and Gate A20 operation
    • Edge trigger or level sensitive interrupt
    • Flash EPROM, 2MB EPROM and combined BIOS support
  • Built-in Nand-tree pin scan test capability
  • 0.5um mixed voltage, high speed and low power CMOS process
  • 208 pin PQFP for VT82C685
  • 208 pin PQFP for VT82C586
  • 208 pin PQFP for VT82C687


The VT82C680 Apollo-P6 is a high performance, cost-effective and energy efficient chip set for the implementation of PCI/ISA desktop and notebook personal computer systems based on the 64-bit Intel Pentium-Pro super-scalar processors. The chipset supports multi-Pentium-Pro configuration with Intel GTL+ driver and receiver interface up to 66Mhz external CPU bus speed. The chipset supports the Pentium-Pro CPU multi-phase bus protocols for split transactions, four level deep in-order queue and deferred transactions for optimal CPU throughput.

Block Diagram

The VT82C680 chip set consists of the VT82C685 system controller, the VT82C687 data buffer and the VT82C586 PCI to ISA bridge. The VT82C680 supports six banks of DRAMs up to 1GB. The DRAM controller supports Standard Page Mode DRAM, EDO-DRAM, Burst EDO-DRAM and Synchronous DRAM in a flexible mixed/match manner. The Burst-EDO and Synchronous DRAM allows zero wait state bursting between the DRAM and the VT82C687 data buffers at 66Mhz. The six banks of DRAM allow arbitrary mixture of 1M/2M/4M/8M/16MxN DRAMs with optional bank-by-bank ECC and parity support. The chipset supports sixteen level (quadwords) of CPU to DRAM write buffers and sixteen level (quadwords) of DRAM to CPU read buffers to maximize the CPU bus and DRAM utilization. The peak data transfer rate for the EDO and Synchronous DRAM (or Burst EDO) DRAMs is 266MB/s and 532MB/s, respectively.

The VT82C680 supports 3.3/5v 32-bit PCI bus with 64-bit to 32-bit data conversion. Sixteen levels (doublewords) of post write buffers are included to allow for concurrent CPU and PCI operation. Consecutive CPU addresses are converted into burst PCI cycles with byte merging capability for optimal CPU to PCI throughput. For PCI master operation, sixteen levels (doublewords) of post write buffers and thirty-two levels (doublewords) of prefetch buffers are included for concurrent PCI bus and DRAM/cache accesses. The chipset also supports enhanced PCI bus commands such as Memory-Read-Line, Memory-Read-Multiple and Memory-Write-Invalid commands to minimize snoop overhead. In addition, the chipset supports advanced features such as snoop ahead, snoop filtering, CPU write-back forward to PCI master and CPU write-back merged with PCI post write buffers to minimize PCI master read latency and DRAM utilization. The VT82C586 PCI to ISA bridge supports four levels (doublewords) of line buffers, type F DMA transfers and delay transaction to allow efficient PCI bus utilization (PCI-2.1 compliant). The VT82C586 also includes integrated keyboard controller with PS2 mouse support, integrated DS12885 style real time clock with extended 128 byte CMOS RAM, integrated master mode enhanced IDE controller with full scatter and gather capability and extension to 33MB/sec UltraDMA-33 transfer rate, integrated USB interface with root hub and two function ports with built-in physical layer transceiver, and OnNow/ACPI compliant advanced configuration and power management interface. A complete main board can be implemented with only six TTLs.

The VT82C680 is ideal for high performance, high quality, high energy efficient and high integration desktop and notebook PCI/ISA computer systems.


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