The BX chipset is out and we can buy the first PC motherboards and CPUs that run at 100 MHz 'front side bus'. Intel tells us that this is the way of the future, but before we just nod we would like to know *why* it's the way of the future or at least *what will it bring us?*. This artcile will once again show that current applications hardly benefit from 100 Mhz 'front side bus' in Slot 1 systems, simply because the most crucial part for the performance of the Pentium II, the L2 cache' is still running at the same speed as before in 66 Mhz 'front side bus' systems. However, AMD is getting ready to release the K6 3d, which will also be using the 100 MHz bus and since the L2 cache is directly linked to the system bus in Socket 7 systems, the performance increase over systems with 66 Mhz bus will be substatially higher.
I only want to give some general ideas why the future will indeed require some RAM that's clocked faster than 66 Mhz. You'll certainly remember the AGP issue, which enables a much higher data bandwidth to the graphical subsystem than PCI used to. One of the theoretical problems of AGP and it's 2x mode is that the peak AGP transfer rate is equal to the peak data bandwith of SDRAM main memory at 66 MHz bus. The AGP will never be accessing the memory on its own, the CPU always wants some of the memory bandwidth as well, so that the theoretical peak bandwidth of 2x AGP mode is nothing but theoretical indeed. Currently there's no software or hardware that takes real advantage of 2x or even higher AGP modes, but finally there will be and this is one reason why we need a higher memory data bandwidth, aquired either with widening of the bus or with higher bus speeds. The other even more important reason why we need faster memory is that clock rates and data processing power of the CPUs are sky rocketing, so that even a large and very fast L2 cache will soon run out of data. CPUs at 500 or more MHz with L2 cache sizes of up to 2 MB running at CPU clock speed will be reality even this year still (Deschutes for Slot 2). Faster CPUs will follow and a higher memory bandwidth will be a lot cheaper than more and more fast L2 cache. Hence there has to be a faster main memory pretty soon and 100 MHz SDRAM is the first step. 200 MHz SDRAM will follow probably before the end of this year, the double data rate SDRAM will first need a CPU that can take advantage of it (currently *zero*), SLDRAM and direct RDRAM that use an unsyncronous memory sub system will join early next year. Merced is supposed to run at 1 GHz and more, so you bet that memory needs to get faster.
Nevertheless does today's software as well as hardware don't urgently require the faster memory speed. Socket 7 systems merely take advantage of the fact that the L2 cache is running at 100 MHz as well, Pentium II systems with their L2 cache running at 1/2 of the CPU speed will not benefit much at all at this point in time.
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